In the prior art, a voltage multiplier using two out-of-phase clock signals to drive a series of capacitors to pump charges through a chain of serially connected MOS transistors acting as a series of diodes to generate a high voltage output is well known. However, because there is a large capacitive loading on the clock signals, it is difficult to drive such a charge pump at a very high frequency clock signals. The typical clock frequency is around 10 MHz. However, the output current of a charge pump or a voltage multiplier is proportional to the operating frequency of the clock signal applied thereto. Thus, the output current I is determined in accordance with I=FC (V.sub.pp -V.sub.t -V.sub.out /n), where F is the frequency of the clock signal, C is the capacitance, V.sub.pp is the peak-to-peak voltage of clock signals, V.sub.t is the threshold of the MOS transistors, V.sub.out is the output voltage, and n is the number of pumping stages. Since there is a limitation in the frequency of the clock signals to drive the voltage multiplier, the current is limited by the capacitance. Capacitance in a semiconductor circuit, however, takes up a large amount of area and thus it is desirable to reduce the capacitance while at the same time maintaining high current output.